Security increasingly depends on hardware, even as we learn the limits of current platforms. Open instruction set architectures like RISC-V promise to lower entry costs and accelerate hardware innovation, while reducing business overhead. Google's silicon root of trust for cloud, Titan is based on RISC-V.
The Linux Foundation CHIPS Alliance supports open-source hardware with high-quality silicon IP, open toolchains and well-verified components. The Open Compute Project (OCP) Open Domain-Specific Architecture (ODSA) group is defining interfaces to package silicon "chiplets" from multiple vendors into domain-specific SoCs.
15 years after inception, the Xen Project stewards a robust, multi-vendor, open-source ecosystem for bare-metal virtualization software. Is there room for Xen in the future landscape of heterogenous, open-source hardware, including RISC-V platforms?
The RISC-V Hypervisor extension specification is progressing along and hopefully there won't be large breaking changes between the current draft version 0.4 and a frozen specification.
Western Digital has been developing a QEMU implementation of the RISC-V Hypervisor extension (based on v0.3) and has ported a baremetal Hypervisor called Xvisor. WDC is working on a KVM port and has done some work towards a Xen port. WDC and Google are both members of https://chipsalliance.org.
Let's discuss how a RISC-V port of Xen can be added to match v0.4 of the evolving specification. This will need to include a full port of Xen as well as adding support to use the Hypervisor extensions. This must be done with upstreaming in mind, to ensure that the RISC-V port will be accepted into mainline Xen, itself a moving target.
(2017) RISC-V Hypervisor extension, https://content.riscv.org/wp-content/uploads/2017/12/Tue0942-riscv-hypervisor-waterman.pdf
(2016) QEMU support for RISC-V, https://www.linux-kvm.org/images/6/6a/02x04B-QEMU-Support_for_the_RISC-V_Instruction_Set_Architecture.pdf